1. Field of the Invention
The invention relates to a semiconductor memory apparatus, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc., and a semiconductor integrated circuit apparatus including the semiconductor memory apparatus.
2. Description of Related Art
Generally, in a semiconductor memory apparatus, a redundancy circuit is provided to realize a redundancy repair function for repairing a defective memory cell being a main cause for reduction in yield rate. In Patent Document 1, the following redundancy circuit structure is adopted. In a memory array having memory cells arranged in a matrix, a redundancy row or a redundancy column that includes a preparatory memory cell capable of replacing a defective memory cell in a circuit is arranged, and a redundancy address is stored in a non-volatile manner by cut-off of a fuse element.
FIG. 22 is a block diagram showing a structure of a memory circuit 100 according to the prior art. In the memory circuit 100 shown in FIG. 22, an address of a defective memory cell is stored, in redundancy fuse circuits 4-1 to 4-4 in a non-volatile manner, as a redundancy address for replacing with a redundancy row or a redundancy column. The redundancy fuse circuits 4-1 to 4-4 may use a metal or polysilicon fuse element blown by laser, or an antifuse applying an excessive gate voltage to a transistor to turn on the transistor, a one-time programmable (OTP) read-only memory cell or a flash memory cell, etc., and are known to have various circuit structures.
FIGS. 23 to 26 are block diagrams showing structures of semiconductor integrated circuit apparatuses according to the prior art. In a semiconductor integrated circuit apparatus of a system on chip (SOC) or an application-specific integrated circuit (ASIC), as shown in FIGS. 23 to 26, there is also known a method of storing a redundancy address in a region other than memory circuits 100A to 100D. In FIG. 23, the redundancy fuse circuits 4-1 to 4-4 are arranged in an external region 220 outside the memory circuit 100A to store a redundancy address, and the redundancy address from the redundancy fuse circuits 4-1 to 4-4 is stored into redundancy address storage circuits 41-1 to 41-4 at power-on.
In the semiconductor integrated circuit apparatuses shown in FIGS. 24 to 26, there is no use of a physical redundancy fuse circuit and the following method is adopted instead. A redundancy address is stored in advance in a flash memory 215 or the like arranged in an external region 200A outside the memory circuits 100B to 100D on a chip. In FIG. 24, the redundancy address stored in the flash memory 215 is stored into the redundancy address storage circuits 41-1 to 41-4 of the memory circuit 100B at power-on. In FIG. 25, a CPU 210 activates redundancy decoders 13-1 to 13-4 of the memory circuit 100C based on the redundancy address stored in the flash memory 215. In FIG. 26, based on the redundancy address stored in the flash memory 215, the CPU 210 separates a normal address and the redundancy address from each other, and outputs the normal address and the redundancy address respectively to an X-decoder 6, a Y-decoder 9 and the redundancy decoders 13-1 to 13-4 of the memory circuit 100D.